1. Technical Field
The present invention is directed generally toward high-density memory architecture and, in particular, to component testing in high-density memories. Still more particularly, the present invention provides a method and architecture for detecting random and systematic transistor degradation for transistor reliability evaluation in high-density memory.
2. Description of the Related Art
In the computer and electronics industry, there is a constant desire to make circuits, particularly integrated circuits, faster and smaller. Making circuits smaller allows many more components to be packed into a chip, increasing functionality and performance. This is particularly true with memory circuits. Increasing the density of components in a memory chip allows for many more memory cells to be fabricated in a memory chip, thus increasing the amount of memory on chip.
However, higher-density circuits pose several problems. In an integrated circuit, components are formed using channels of highly doped silicon, channels of polysilicon, and layers of insulation. Recently, the channel lengths have decreased from 400 nanometers (nm) to as small as 90 nm and will likely decrease even further. These small channel lengths allow components, particularly transistors, to be tightly packed. However, with these small channel lengths transistors and other components become more difficult to fabricate without defects.
A traditional reliability test is the hot carrier injection (HCI) test on a single transistor. This test can extensively study the various degradation mechanisms on a transistor, such as threshold voltage shift and channel leakage current. This test can also provide information on the possible process weaknesses relating to a certain degradation and hint for improvements. Yet this single transistor case may not be able to indicate the failure possibility in millions to billions of transistors on the chip.
A wafer may have fabricated thereon as many as a few tens of instances of a circuit. Thus, when testing a single transistor, only a few tens of transistors will be tested on a wafer, one from each circuit. However, defects are typically random and the probability of detecting a defect using a single transistor test is very low.
Moreover, transistors in high-density memory may behave differently than a single transistor, even drawn with the same size, due to the different environment and density. Even by measuring many transistors from these single-transistor instances, the data may not represent exactly the possible weakness or defect in the transistors in the high-density memory. Furthermore, the existing physical failure analysis process (such as parallel capping or cross-sectioning of failing circuits) used to detect and analyze defects and degradations is usually time-consuming. Hence, quick feedback to process development is not possible with these techniques. Therefore, it would be advantageous to provide an improved method and architecture which is able to detect random and systematic transistor defects and degradation within the millions of transistors in the high-density memory circuit and in the very early stage of the process development.